The present invention relates to common mode logic (CML) circuits and, in particular, to parallel clocked CML latch circuits.
Latch circuits have numerous applications and are well known in the art. A latch circuit typically consists of an acquire stage and a regeneration stage where data is clocked into the acquire stage when a clock is in a first logic state and then stored in the regeneration stage when the clock is in a second logic state as is known. Furthermore, the acquire stage can also provide an AND gate function that is typically comprised of a predetermined number of gating levels such that the number of gating levels corresponds to the number of differential inputs to the AND gate. Therefore, a two-input AND gate has differentially coupled transistors configured such that the source electrodes of the first and second transistors of the first gating level are coupled to the drain electrode of a first transistor of a second gating level while the drain electrode of the second transistor of the second gating level is coupled to the drain electrode of the second transistor of the first gating level. Also, the drain electrodes of the first and second transistors of the first gating level are coupled to a supply voltage terminal through separate resistors and the source electrodes of the first and second transistors of the second gating level are coupled to an independent or constant current source. In addition, the gate electrodes of the first and second transistors of the first gating level are typically coupled to a first differential input signal while the gate electrodes of the first and second transistors of the second gating level are typically coupled to a second differential input signal. Further, this configuration can be expanded to a plurality of different gating levels configured in a similar aforedescribed manner thereby providing an AND gate having a plurality of differential inputs as is known. Hence, as an example, a three-input AND gate would require three levels of gating such that if all non-inverting inputs to the AND gate are a logic high, then a non-inverting output of the latch circuit will also be a logic high as is understood.
Most, if not all, prior art has performed the clock function of the latch circuit by adding an extra gating level that is coupled to the lowest gating level of the AND gate in a similar aforedescribed manner as the different levels are configured in the AND gate. Therefore, the clock gating level typically includes a pair of differentially coupled transistors such that the drain electrode of the first transistor of the clock gating level is coupled to the source electrodes of the first and second transistors of the lowest gating level of the AND gate while the drain electrode of the second transistor of the clock gating level is coupled to the regeneration stage of the latch circuit. Further, the source electrodes of the first and second transistors of the clock gating level are now coupled to the independent or constant current source while the gate electrodes of the same are coupled to a differential clock signal. Thus, when the differential clock is in a first logic state, the first transistor of the clock gating level is turned on thereby rendering the acquire stage (AND gate) operative. Furthermore, when the differential clock is in a second logic state, the second transistor of the clock gating level is turned on thereby rendering the regeneration stage operative as is understood. However, since each gating level requires a substantial amount of current, the number of gating levels in the latch circuit is directly proportional to the power dissipated. Therefore, if the clock function of the latch circuit could be provided in parallel with the AND gate and, thus, abating the addition of an extra clock gating level, a substantial power reduction would result along with a decrease in device count.
Hence, a need exists for a parallel clocked latch circuit having minimum power and minimum device count.